Semiconductor devices such as integrated circuits (ICs) are fabricated in or on a surface of a semiconductor substrate or wafer that is subsequently divided or diced into a number of discrete chips or dies each having a device or IC formed thereon. One or more dies are then enclosed in a package that provides physical and electrical protection of the die(s) while electrically connecting it with external circuits, devices and power supplies. Packages for semiconductor devices are available in the very wide variety of designs depending on the desired electrical connections out of the package, desired heat dissipation or thermal conductivity, and other physical requirements, such as optical transparency.
Conventional molded packages, such as that shown in FIGS. 1A and 1B are produced by attaching the die or chip 100 to a flag or paddle 102 of a leadframe 104, and electrically coupling circuit elements on the chip to lead fingers or leads 106 using a bonding wire 108. Typically, the leadframe 104 with the attached chip 100 is then encapsulated in a plastic molding compound to form a package body or package 110 using an injection or transfer molding process.
One problem with the conventional packaging technology shown in FIGS. 1A and 1B, known as epoxy chip bonding, is that the maximum allowable size or dimension (D) of the chip 100 in the package 110 is equal to or smaller than the size of the paddle 104 (P). In particular, referring to FIG. 1A it is seen that the maximum allowable dimension of the chip 100 within the package 110 is limited as expressed by the following equation:D=B−2(L+b+a)  (Eq. 1)where D is the maximum allowable chip dimension, B is a size or dimension of the package 110, L is a length of the leads 106 inside the package body, b is a spacing or separation between the leads and the paddle 102, and a is a distance from an edge of the chip to an edge of the paddle.
For certain advanced packaging technologies (not shown) the chip 100 can be very precisely centered on the paddle 102, thereby enabling the chip to paddle edge distance or spacing (denoted by a in FIG. 1A) to be eliminated, and facilitating the packaging of slightly larger chips as express by equation no. 2:D=B−2(L+b)  (Eq. 2)
It will be appreciated that even with these advanced technologies the conventional packages and packaging method impose severe constraints on the maximum allowable chip dimensions, and/or on a minimum allowable package size.
Another conventional packaging method, shown in FIGS. 2A and 2B, intended to permit packaging of larger chip sizes uses a Chip-On-Lead (COL) technology. Referring to FIGS. 2A and 2B, the COL packaging method includes a step of laminating a backside or surface of a chip 200 with an electrically insulating material 202, such as a non-conductive adhesive, and attaching it directly to leads 204 of a leadframe 206 eliminating the need for a paddle in the leadframe altogether. Pads on the chip are then reverse wire bonded 208 to the leads 204, and the leadframe 206 with the chip mounted thereon encapsulated in a molding compound to form the package body 210. This approach does accommodate a larger chip size, however an assembly unit cost for devices or ICs packaged using COL technology is relatively higher than for the approach shown in FIGS. 1A and 1B due to the expense of an additional lamination step, and the cost of electrically insulating material 202 and capital equipment cost of tools for performing the lamination step.
Accordingly, there is a need for a package and packaging method for semiconductor devices and ICs that addresses maximum chip size constraints, thereby enabling packaging of larger chips and/or the use of smaller packages without substantially increasing the assembly unit cost for the packaged devices. It is further desirable that the package and packaging method are compatible with automated backend assembly or packaging process.